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A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS

Abstract: 

This paper presents an LDPC decoder employing a column-parallel architecture that enables low-power and high-speed operation suitable for the 802.11ad standard. As compared to the conventional row-parallel architecture, the proposed architecture reduces the required memory size by 60% and also minimizes the number of pipeline stages for high throughput operation. Fabricated in 40nm LP CMOS technology, the prototype achieves high energy efficiency of 4.7pJ/bit/iteration for 6.16Gb/s while supporting all the modulation and coding schemes (MCS0 to MCS12) required for the 802.11ad single-carrier (SC) modulation.

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Paper Details

Authors:
Naoya Yosoku, Takenori Sakamoto, Takayuki Tsukizawa, Naganori Shirakata, Koji Takinami
Submitted On:
23 February 2016 - 1:44pm
Short Link:
Type:
Presentation Slides
Event:
Presenter's Name:
Hiroyuki Motozuka
Document Year:
2015
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Document Files

GlobalSIP2015_motozuka_r6.pdf

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[1] Naoya Yosoku, Takenori Sakamoto, Takayuki Tsukizawa, Naganori Shirakata, Koji Takinami, "A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS", IEEE SigPort, 2015. [Online]. Available: http://sigport.org/378. Accessed: May. 21, 2018.
@article{378-15,
url = {http://sigport.org/378},
author = {Naoya Yosoku; Takenori Sakamoto; Takayuki Tsukizawa; Naganori Shirakata; Koji Takinami },
publisher = {IEEE SigPort},
title = {A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS},
year = {2015} }
TY - EJOUR
T1 - A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS
AU - Naoya Yosoku; Takenori Sakamoto; Takayuki Tsukizawa; Naganori Shirakata; Koji Takinami
PY - 2015
PB - IEEE SigPort
UR - http://sigport.org/378
ER -
Naoya Yosoku, Takenori Sakamoto, Takayuki Tsukizawa, Naganori Shirakata, Koji Takinami. (2015). A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS. IEEE SigPort. http://sigport.org/378
Naoya Yosoku, Takenori Sakamoto, Takayuki Tsukizawa, Naganori Shirakata, Koji Takinami, 2015. A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS. Available at: http://sigport.org/378.
Naoya Yosoku, Takenori Sakamoto, Takayuki Tsukizawa, Naganori Shirakata, Koji Takinami. (2015). "A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS." Web.
1. Naoya Yosoku, Takenori Sakamoto, Takayuki Tsukizawa, Naganori Shirakata, Koji Takinami. A 6.16Gb/s 4.7pJ/bit/iteration LDPC decoder for IEEE 802.11ad standard in 40nm LP-CMOS [Internet]. IEEE SigPort; 2015. Available from : http://sigport.org/378