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System-on-chip architectures for signal processing

Implementation of Efficient, Low Power Deep Neural Networks on Next-Generation Intel Client Platforms


ICASSP 2017 Demonstration

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Authors:
Michael Deisher, Andrzej Polonski
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12 April 2017 - 10:44am
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PosterFinal.pdf

(257 downloads)

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[1] Michael Deisher, Andrzej Polonski, "Implementation of Efficient, Low Power Deep Neural Networks on Next-Generation Intel Client Platforms", IEEE SigPort, 2017. [Online]. Available: http://sigport.org/1777. Accessed: Nov. 23, 2017.
@article{1777-17,
url = {http://sigport.org/1777},
author = {Michael Deisher; Andrzej Polonski },
publisher = {IEEE SigPort},
title = {Implementation of Efficient, Low Power Deep Neural Networks on Next-Generation Intel Client Platforms},
year = {2017} }
TY - EJOUR
T1 - Implementation of Efficient, Low Power Deep Neural Networks on Next-Generation Intel Client Platforms
AU - Michael Deisher; Andrzej Polonski
PY - 2017
PB - IEEE SigPort
UR - http://sigport.org/1777
ER -
Michael Deisher, Andrzej Polonski. (2017). Implementation of Efficient, Low Power Deep Neural Networks on Next-Generation Intel Client Platforms. IEEE SigPort. http://sigport.org/1777
Michael Deisher, Andrzej Polonski, 2017. Implementation of Efficient, Low Power Deep Neural Networks on Next-Generation Intel Client Platforms. Available at: http://sigport.org/1777.
Michael Deisher, Andrzej Polonski. (2017). "Implementation of Efficient, Low Power Deep Neural Networks on Next-Generation Intel Client Platforms." Web.
1. Michael Deisher, Andrzej Polonski. Implementation of Efficient, Low Power Deep Neural Networks on Next-Generation Intel Client Platforms [Internet]. IEEE SigPort; 2017. Available from : http://sigport.org/1777

Multicore Digital Signal Processor for Heterogeneous Systems Era


Heterogeneous processing represents the future of computing, promising to unlock the performance and power efficiency of the parallel computing engines found in most modern electronic devices. This talk will detail the HSA computing platform infrastructure including features/advantages across computing platforms from mobile and tablets to desktops to HPC and servers. The talk will focus on technical issues mapping DSPs to HSA systems using GPT's new DSP processor as a representative example.

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23 February 2016 - 1:44pm
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global_sip_keynote_2015_12_16_final_distribution.pdf

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[1] , "Multicore Digital Signal Processor for Heterogeneous Systems Era", IEEE SigPort, 2015. [Online]. Available: http://sigport.org/568. Accessed: Nov. 23, 2017.
@article{568-15,
url = {http://sigport.org/568},
author = { },
publisher = {IEEE SigPort},
title = {Multicore Digital Signal Processor for Heterogeneous Systems Era},
year = {2015} }
TY - EJOUR
T1 - Multicore Digital Signal Processor for Heterogeneous Systems Era
AU -
PY - 2015
PB - IEEE SigPort
UR - http://sigport.org/568
ER -
. (2015). Multicore Digital Signal Processor for Heterogeneous Systems Era. IEEE SigPort. http://sigport.org/568
, 2015. Multicore Digital Signal Processor for Heterogeneous Systems Era. Available at: http://sigport.org/568.
. (2015). "Multicore Digital Signal Processor for Heterogeneous Systems Era." Web.
1. . Multicore Digital Signal Processor for Heterogeneous Systems Era [Internet]. IEEE SigPort; 2015. Available from : http://sigport.org/568

Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture

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Authors:
Tobias Linde, Holger Blume
Submitted On:
23 February 2016 - 1:44pm
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2015-12-16_GlobalSIP15_Arndt.pdf

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[1] Tobias Linde, Holger Blume, "Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture", IEEE SigPort, 2015. [Online]. Available: http://sigport.org/321. Accessed: Nov. 23, 2017.
@article{321-15,
url = {http://sigport.org/321},
author = {Tobias Linde; Holger Blume },
publisher = {IEEE SigPort},
title = {Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture},
year = {2015} }
TY - EJOUR
T1 - Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture
AU - Tobias Linde; Holger Blume
PY - 2015
PB - IEEE SigPort
UR - http://sigport.org/321
ER -
Tobias Linde, Holger Blume. (2015). Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture. IEEE SigPort. http://sigport.org/321
Tobias Linde, Holger Blume, 2015. Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture. Available at: http://sigport.org/321.
Tobias Linde, Holger Blume. (2015). "Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture." Web.
1. Tobias Linde, Holger Blume. Implementation and Analysis of the Histograms of Oriented Gradients Algorithm on a Heterogeneous Multicore CPU/GPU Architecture [Internet]. IEEE SigPort; 2015. Available from : http://sigport.org/321