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Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems

Abstract: 

Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a ``simple'' replacement of eFlash in micro-controller and introducing RRAM inside the memory hierarchy is not a straightforward move. Indeed, integrating a RRAM technology inside the cache hierarchy requires higher endurance requirement than for eFlash replacement, and thus necessitates relaxed programming conditions. By doing so, the reliability bottleneck is moved from programming to the read operations (i.e., read margin is reduced and the risk of read failure is increased). Based on this observation, in this work, we propose to explore how Edge-level applications running on a RRAM-based Edge device could fail because of Bias Temperature Instability (BTI). BTI causes threshold voltage (Vt) degradation on the transistors along the memory WordLines (WL), leading to a reduction of the read margin along regularly used WLs. We thereby propose a 3-steps methodology consisting in (i) characterizing the RRAM bitcell and identifying beyond which Vt shift the read operation is going to fail. (ii) characterizing applications and extracting the memory traces. And (iii) running a long term BTI simulation to extract the actual Vt shift of the bitcells sharing the same array WordLine. Based on this, we show that for a 1T1R bitcell featuring a 250% High/Low Resistance State (HRS/LRS) ratio, read failures tend to happen after less than a month in the case of a constantly running convolution kernel. These simulations highlight the fact that transistor-level reliability can be critical for embedded RRAM and that specific workload aware simulation frameworks are required to assess their effects.

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Paper Details

Authors:
Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza
Submitted On:
4 February 2020 - 8:19am
Short Link:
Type:
Research Manuscript
Event:
Presenter's Name:
Levisse
Paper Code:
3904
Document Year:
2020
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[1] Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza, "Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/4971. Accessed: Aug. 08, 2020.
@article{4971-20,
url = {http://sigport.org/4971},
author = {Alexandre Levisse; Marco Rios; Miguel Peon; David Atienza },
publisher = {IEEE SigPort},
title = {Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems},
year = {2020} }
TY - EJOUR
T1 - Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems
AU - Alexandre Levisse; Marco Rios; Miguel Peon; David Atienza
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/4971
ER -
Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza. (2020). Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. IEEE SigPort. http://sigport.org/4971
Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza, 2020. Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. Available at: http://sigport.org/4971.
Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza. (2020). "Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems." Web.
1. Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza. Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/4971