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Design and Implementation of Signal Processing Systems

Application Informed Motion Signal Processing for Finger Motion Tracking Using Wearable Sensors

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Authors:
Yilin Liu, Fengyang Jiang, Mahanth Gowda
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25 May 2020 - 11:40pm
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ICASSP2020 FinGTrAC.pdf

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[1] Yilin Liu, Fengyang Jiang, Mahanth Gowda, "Application Informed Motion Signal Processing for Finger Motion Tracking Using Wearable Sensors", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/5435. Accessed: Sep. 25, 2020.
@article{5435-20,
url = {http://sigport.org/5435},
author = {Yilin Liu; Fengyang Jiang; Mahanth Gowda },
publisher = {IEEE SigPort},
title = {Application Informed Motion Signal Processing for Finger Motion Tracking Using Wearable Sensors},
year = {2020} }
TY - EJOUR
T1 - Application Informed Motion Signal Processing for Finger Motion Tracking Using Wearable Sensors
AU - Yilin Liu; Fengyang Jiang; Mahanth Gowda
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/5435
ER -
Yilin Liu, Fengyang Jiang, Mahanth Gowda. (2020). Application Informed Motion Signal Processing for Finger Motion Tracking Using Wearable Sensors. IEEE SigPort. http://sigport.org/5435
Yilin Liu, Fengyang Jiang, Mahanth Gowda, 2020. Application Informed Motion Signal Processing for Finger Motion Tracking Using Wearable Sensors. Available at: http://sigport.org/5435.
Yilin Liu, Fengyang Jiang, Mahanth Gowda. (2020). "Application Informed Motion Signal Processing for Finger Motion Tracking Using Wearable Sensors." Web.
1. Yilin Liu, Fengyang Jiang, Mahanth Gowda. Application Informed Motion Signal Processing for Finger Motion Tracking Using Wearable Sensors [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/5435

Soft-Output Finite Alphabet Equalization for mmWave Massive MIMO

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Authors:
Oscar Castañeda, Sven Jacobsson, Giuseppe Durisi, Tom Goldstein, Christoph Studer
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15 May 2020 - 4:41pm
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20ICASSP_SoftFAME_release.pdf

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[1] Oscar Castañeda, Sven Jacobsson, Giuseppe Durisi, Tom Goldstein, Christoph Studer, "Soft-Output Finite Alphabet Equalization for mmWave Massive MIMO", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/5353. Accessed: Sep. 25, 2020.
@article{5353-20,
url = {http://sigport.org/5353},
author = {Oscar Castañeda; Sven Jacobsson; Giuseppe Durisi; Tom Goldstein; Christoph Studer },
publisher = {IEEE SigPort},
title = {Soft-Output Finite Alphabet Equalization for mmWave Massive MIMO},
year = {2020} }
TY - EJOUR
T1 - Soft-Output Finite Alphabet Equalization for mmWave Massive MIMO
AU - Oscar Castañeda; Sven Jacobsson; Giuseppe Durisi; Tom Goldstein; Christoph Studer
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/5353
ER -
Oscar Castañeda, Sven Jacobsson, Giuseppe Durisi, Tom Goldstein, Christoph Studer. (2020). Soft-Output Finite Alphabet Equalization for mmWave Massive MIMO. IEEE SigPort. http://sigport.org/5353
Oscar Castañeda, Sven Jacobsson, Giuseppe Durisi, Tom Goldstein, Christoph Studer, 2020. Soft-Output Finite Alphabet Equalization for mmWave Massive MIMO. Available at: http://sigport.org/5353.
Oscar Castañeda, Sven Jacobsson, Giuseppe Durisi, Tom Goldstein, Christoph Studer. (2020). "Soft-Output Finite Alphabet Equalization for mmWave Massive MIMO." Web.
1. Oscar Castañeda, Sven Jacobsson, Giuseppe Durisi, Tom Goldstein, Christoph Studer. Soft-Output Finite Alphabet Equalization for mmWave Massive MIMO [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/5353

Can every analog system be simulated on a digital computer?


A Turing machine is a model describing the fundamental limits of any realizable computer, digital signal processor (DSP), or field programmable gate array (FPGA). This paper shows that there exist very simple linear time-invariant (LTI) systems which can not be simulated on a Turing machine. In particular, this paper considers the linear system described by the voltage-current relation of an ideal capacitor. For this system, it is shown that there exist continuously differentiable and computable input signals such that the output signal is a continuous function which is not computable.

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14 May 2020 - 6:54am
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BoPo_ICASSP2597.pdf

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[1] , "Can every analog system be simulated on a digital computer?", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/5281. Accessed: Sep. 25, 2020.
@article{5281-20,
url = {http://sigport.org/5281},
author = { },
publisher = {IEEE SigPort},
title = {Can every analog system be simulated on a digital computer?},
year = {2020} }
TY - EJOUR
T1 - Can every analog system be simulated on a digital computer?
AU -
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/5281
ER -
. (2020). Can every analog system be simulated on a digital computer?. IEEE SigPort. http://sigport.org/5281
, 2020. Can every analog system be simulated on a digital computer?. Available at: http://sigport.org/5281.
. (2020). "Can every analog system be simulated on a digital computer?." Web.
1. . Can every analog system be simulated on a digital computer? [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/5281

Slides of my paper in ICASSP2020: Greedy Hybrid Rate Adaptation in Dynamic Wireless Communication environment

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13 May 2020 - 10:26pm
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slides_ICASSP2020.pdf

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[1] , "Slides of my paper in ICASSP2020: Greedy Hybrid Rate Adaptation in Dynamic Wireless Communication environment", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/5171. Accessed: Sep. 25, 2020.
@article{5171-20,
url = {http://sigport.org/5171},
author = { },
publisher = {IEEE SigPort},
title = {Slides of my paper in ICASSP2020: Greedy Hybrid Rate Adaptation in Dynamic Wireless Communication environment},
year = {2020} }
TY - EJOUR
T1 - Slides of my paper in ICASSP2020: Greedy Hybrid Rate Adaptation in Dynamic Wireless Communication environment
AU -
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/5171
ER -
. (2020). Slides of my paper in ICASSP2020: Greedy Hybrid Rate Adaptation in Dynamic Wireless Communication environment. IEEE SigPort. http://sigport.org/5171
, 2020. Slides of my paper in ICASSP2020: Greedy Hybrid Rate Adaptation in Dynamic Wireless Communication environment. Available at: http://sigport.org/5171.
. (2020). "Slides of my paper in ICASSP2020: Greedy Hybrid Rate Adaptation in Dynamic Wireless Communication environment." Web.
1. . Slides of my paper in ICASSP2020: Greedy Hybrid Rate Adaptation in Dynamic Wireless Communication environment [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/5171

Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture

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Jian Zhou, Subhankar Pal, David Blaauw, Hun Seok Kim, Trevor Mudge, Ronald Dreslinski, Chaitali Chakrabarti
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1 May 2020 - 8:36pm
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soorishetty.pdf

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[1] Jian Zhou, Subhankar Pal, David Blaauw, Hun Seok Kim, Trevor Mudge, Ronald Dreslinski, Chaitali Chakrabarti, "Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/5116. Accessed: Sep. 25, 2020.
@article{5116-20,
url = {http://sigport.org/5116},
author = {Jian Zhou; Subhankar Pal; David Blaauw; Hun Seok Kim; Trevor Mudge; Ronald Dreslinski; Chaitali Chakrabarti },
publisher = {IEEE SigPort},
title = {Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture},
year = {2020} }
TY - EJOUR
T1 - Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture
AU - Jian Zhou; Subhankar Pal; David Blaauw; Hun Seok Kim; Trevor Mudge; Ronald Dreslinski; Chaitali Chakrabarti
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/5116
ER -
Jian Zhou, Subhankar Pal, David Blaauw, Hun Seok Kim, Trevor Mudge, Ronald Dreslinski, Chaitali Chakrabarti. (2020). Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture. IEEE SigPort. http://sigport.org/5116
Jian Zhou, Subhankar Pal, David Blaauw, Hun Seok Kim, Trevor Mudge, Ronald Dreslinski, Chaitali Chakrabarti, 2020. Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture. Available at: http://sigport.org/5116.
Jian Zhou, Subhankar Pal, David Blaauw, Hun Seok Kim, Trevor Mudge, Ronald Dreslinski, Chaitali Chakrabarti. (2020). "Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture." Web.
1. Jian Zhou, Subhankar Pal, David Blaauw, Hun Seok Kim, Trevor Mudge, Ronald Dreslinski, Chaitali Chakrabarti. Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/5116

Denoising Deep Boltzmann Machines: Compression for Deep Learning

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19 April 2020 - 4:46pm
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[1] , "Denoising Deep Boltzmann Machines: Compression for Deep Learning", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/5036. Accessed: Sep. 25, 2020.
@article{5036-20,
url = {http://sigport.org/5036},
author = { },
publisher = {IEEE SigPort},
title = {Denoising Deep Boltzmann Machines: Compression for Deep Learning},
year = {2020} }
TY - EJOUR
T1 - Denoising Deep Boltzmann Machines: Compression for Deep Learning
AU -
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/5036
ER -
. (2020). Denoising Deep Boltzmann Machines: Compression for Deep Learning. IEEE SigPort. http://sigport.org/5036
, 2020. Denoising Deep Boltzmann Machines: Compression for Deep Learning. Available at: http://sigport.org/5036.
. (2020). "Denoising Deep Boltzmann Machines: Compression for Deep Learning." Web.
1. . Denoising Deep Boltzmann Machines: Compression for Deep Learning [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/5036

Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors


Quantum computers threaten to break public-key cryptography schemes such as DSA and ECDSA in polynomial time, which poses an imminent threat to secure signal processing.
Ring learning with error (RLWE) lattice-based cryptography (LBC) is one of the most promising families of post-quantum cryptography (PQC) schemes in terms of efficiency and versatility. Two conventional methods to compute polynomial multiplication, the most compute-intensive routine in the RLWE schemes, are convolutions and Number Theoretic Transform (NTT).

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Authors:
Hamid Nejatollahi, Sina Shahhosseini, Rosario Cammarota, Nikil Dutt
Submitted On:
12 February 2020 - 8:32pm
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2020_ICASSP-Camera_ready.pdf

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[1] Hamid Nejatollahi, Sina Shahhosseini, Rosario Cammarota, Nikil Dutt, "Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/4985. Accessed: Sep. 25, 2020.
@article{4985-20,
url = {http://sigport.org/4985},
author = {Hamid Nejatollahi; Sina Shahhosseini; Rosario Cammarota; Nikil Dutt },
publisher = {IEEE SigPort},
title = {Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors},
year = {2020} }
TY - EJOUR
T1 - Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors
AU - Hamid Nejatollahi; Sina Shahhosseini; Rosario Cammarota; Nikil Dutt
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/4985
ER -
Hamid Nejatollahi, Sina Shahhosseini, Rosario Cammarota, Nikil Dutt. (2020). Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors. IEEE SigPort. http://sigport.org/4985
Hamid Nejatollahi, Sina Shahhosseini, Rosario Cammarota, Nikil Dutt, 2020. Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors. Available at: http://sigport.org/4985.
Hamid Nejatollahi, Sina Shahhosseini, Rosario Cammarota, Nikil Dutt. (2020). "Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors." Web.
1. Hamid Nejatollahi, Sina Shahhosseini, Rosario Cammarota, Nikil Dutt. Exploring Energy Efficient Quantum-resistant Signal Processing Using Array Processors [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/4985

Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems


Resistive switching memory technologies (RRAM) are seen by most of the scientific community as an enabler for Edge-level applications such as embedded deep Learning, AI or signal processing of audio and video signals. However, going beyond a ``simple'' replacement of eFlash in micro-controller and introducing RRAM inside the memory hierarchy is not a straightforward move. Indeed, integrating a RRAM technology inside the cache hierarchy requires higher endurance requirement than for eFlash replacement, and thus necessitates relaxed programming conditions.

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Authors:
Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza
Submitted On:
4 February 2020 - 8:19am
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ICASSP_VF.pdf

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[1] Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza, "Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems", IEEE SigPort, 2020. [Online]. Available: http://sigport.org/4971. Accessed: Sep. 25, 2020.
@article{4971-20,
url = {http://sigport.org/4971},
author = {Alexandre Levisse; Marco Rios; Miguel Peon; David Atienza },
publisher = {IEEE SigPort},
title = {Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems},
year = {2020} }
TY - EJOUR
T1 - Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems
AU - Alexandre Levisse; Marco Rios; Miguel Peon; David Atienza
PY - 2020
PB - IEEE SigPort
UR - http://sigport.org/4971
ER -
Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza. (2020). Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. IEEE SigPort. http://sigport.org/4971
Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza, 2020. Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. Available at: http://sigport.org/4971.
Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza. (2020). "Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems." Web.
1. Alexandre Levisse, Marco Rios, Miguel Peon, David Atienza. Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems [Internet]. IEEE SigPort; 2020. Available from : http://sigport.org/4971

STOCHASTIC DATA-DRIVEN HARDWARE RESILIENCE TO EFFICIENTLY TRAIN INFERENCE MODELS FOR STOCHASTIC HARDWARE IMPLEMENTATIONS


Machine-learning algorithms are being employed in an increasing range of applications, spanning high-performance and energy-constrained platforms. It has been noted that the statistical nature of the algorithms can open up new opportunities for throughput and energy efficiency, by moving hardware into design regimes not limited to deterministic models of computation. This work aims to enable high accuracy in machine-learning inference systems, where computations are substantially affected by hardware variability.

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Authors:
Bonan Zhang, Lung-Yen Chen, Naveen Verma
Submitted On:
10 May 2019 - 12:07am
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ZhangChenVerma_ICASSP2019.pdf

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[1] Bonan Zhang, Lung-Yen Chen, Naveen Verma, "STOCHASTIC DATA-DRIVEN HARDWARE RESILIENCE TO EFFICIENTLY TRAIN INFERENCE MODELS FOR STOCHASTIC HARDWARE IMPLEMENTATIONS", IEEE SigPort, 2019. [Online]. Available: http://sigport.org/4265. Accessed: Sep. 25, 2020.
@article{4265-19,
url = {http://sigport.org/4265},
author = {Bonan Zhang; Lung-Yen Chen; Naveen Verma },
publisher = {IEEE SigPort},
title = {STOCHASTIC DATA-DRIVEN HARDWARE RESILIENCE TO EFFICIENTLY TRAIN INFERENCE MODELS FOR STOCHASTIC HARDWARE IMPLEMENTATIONS},
year = {2019} }
TY - EJOUR
T1 - STOCHASTIC DATA-DRIVEN HARDWARE RESILIENCE TO EFFICIENTLY TRAIN INFERENCE MODELS FOR STOCHASTIC HARDWARE IMPLEMENTATIONS
AU - Bonan Zhang; Lung-Yen Chen; Naveen Verma
PY - 2019
PB - IEEE SigPort
UR - http://sigport.org/4265
ER -
Bonan Zhang, Lung-Yen Chen, Naveen Verma. (2019). STOCHASTIC DATA-DRIVEN HARDWARE RESILIENCE TO EFFICIENTLY TRAIN INFERENCE MODELS FOR STOCHASTIC HARDWARE IMPLEMENTATIONS. IEEE SigPort. http://sigport.org/4265
Bonan Zhang, Lung-Yen Chen, Naveen Verma, 2019. STOCHASTIC DATA-DRIVEN HARDWARE RESILIENCE TO EFFICIENTLY TRAIN INFERENCE MODELS FOR STOCHASTIC HARDWARE IMPLEMENTATIONS. Available at: http://sigport.org/4265.
Bonan Zhang, Lung-Yen Chen, Naveen Verma. (2019). "STOCHASTIC DATA-DRIVEN HARDWARE RESILIENCE TO EFFICIENTLY TRAIN INFERENCE MODELS FOR STOCHASTIC HARDWARE IMPLEMENTATIONS." Web.
1. Bonan Zhang, Lung-Yen Chen, Naveen Verma. STOCHASTIC DATA-DRIVEN HARDWARE RESILIENCE TO EFFICIENTLY TRAIN INFERENCE MODELS FOR STOCHASTIC HARDWARE IMPLEMENTATIONS [Internet]. IEEE SigPort; 2019. Available from : http://sigport.org/4265

SVM-based Seal Imprint Verification Using Edge Difference

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9 May 2019 - 9:29pm
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[1] , "SVM-based Seal Imprint Verification Using Edge Difference", IEEE SigPort, 2019. [Online]. Available: http://sigport.org/4250. Accessed: Sep. 25, 2020.
@article{4250-19,
url = {http://sigport.org/4250},
author = { },
publisher = {IEEE SigPort},
title = {SVM-based Seal Imprint Verification Using Edge Difference},
year = {2019} }
TY - EJOUR
T1 - SVM-based Seal Imprint Verification Using Edge Difference
AU -
PY - 2019
PB - IEEE SigPort
UR - http://sigport.org/4250
ER -
. (2019). SVM-based Seal Imprint Verification Using Edge Difference. IEEE SigPort. http://sigport.org/4250
, 2019. SVM-based Seal Imprint Verification Using Edge Difference. Available at: http://sigport.org/4250.
. (2019). "SVM-based Seal Imprint Verification Using Edge Difference." Web.
1. . SVM-based Seal Imprint Verification Using Edge Difference [Internet]. IEEE SigPort; 2019. Available from : http://sigport.org/4250

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