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FFTTA presentation

Abstract: 

This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations. The power savings are achieved by compressing the computation kernel into one instruction word. The word is stored in an instruction loop buffer, which is more power-efficient than regular instruction memory storage. The processor supports all power-of-two FFT sizes from 64 to 16384 and given 1 mJ of energy, it can compute 20916 transforms of size 1024.

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Paper Details

Authors:
Submitted On:
14 May 2019 - 8:31am
Short Link:
Type:
Presentation Slides
Event:
Presenter's Name:
Jakub Žádník
Paper Code:
3342
Document Year:
2019
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Document Files

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[1] , "FFTTA presentation", IEEE SigPort, 2019. [Online]. Available: http://sigport.org/4345. Accessed: Aug. 25, 2019.
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url = {http://sigport.org/4345},
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publisher = {IEEE SigPort},
title = {FFTTA presentation},
year = {2019} }
TY - EJOUR
T1 - FFTTA presentation
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PY - 2019
PB - IEEE SigPort
UR - http://sigport.org/4345
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. (2019). FFTTA presentation. IEEE SigPort. http://sigport.org/4345
, 2019. FFTTA presentation. Available at: http://sigport.org/4345.
. (2019). "FFTTA presentation." Web.
1. . FFTTA presentation [Internet]. IEEE SigPort; 2019. Available from : http://sigport.org/4345