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We develop a new multiple input multiple output (MIMO) transceiver architecture – Differential Beamspace MIMO (DB-MIMO) for high-dimensional MIMO systems. DB- MIMO enables linear quasi-coherent interference suppression between multiple spatially multiplexed data streams in con- junction with differential transmission. The differential nature of DB-MIMO is particularly attractive in emerging high- frequency systems, e.g. centimeter-wave (cmW) and millimeter- wave (mmW) systems, where the requirement of a phase- coherent local oscillator at the receiver can be challenging.

Robustness is an important and challenging issue in internet of things (IoT), where contains multiple types of heterogeneous networks. To solve this problem, we design and realize a greedy model with small world properties (GMSW) for heterogeneous sensor network of IoT. In GMSW, two greedy criteria are presented firstly, which are used to distinguish importance of different network nodes. On the basis, we define the concept of local importance of node and design a shortcut-added strategy, by which way prompts the network present small world phenomenon.

In this paper, we design a heuristic interference-graph-based time division multiple access (IG-TDMA) protocol for underwater acoustic sensor networks (UW-ASNs) to improve the network performance.

For more information, please check out the publication at IEEE Xplore:

X. Cheng, R. Zhang, L. Yang, and X. Cheng “Heuristic IG-TDMA Protocol for Underwater Acoustic Sensor Networks," in Proceedings of 2015 IEEE Global Conference on Signal and Information Processing, Orlando, Florida, Dec. 14 - 16, 2015.

This is the presentation slide for GlobalSIP 2015. Our accepted paper title is "Optical Interference Alignment for an Indoor Visible Light Communication X-Channel".

This paper presents an LDPC decoder employing a column-parallel architecture that enables low-power and high-speed operation suitable for the 802.11ad standard. As compared to the conventional row-parallel architecture, the proposed architecture reduces the required memory size by 60% and also minimizes the number of pipeline stages for high throughput operation.